1. Technical Field
The present disclosure relates to electronic circuits and, more particularly, to delay cells capable of improving characteristics of an output signal and delay line circuits having the delay cells.
2. Discussion of Related Art
A delay line circuit introduces a predetermined delay into the transmission of a signal. A delay line circuit generally includes a plurality of delay cells connected in series. A delay line circuit is widely used as a delay-locked loop circuit for generating clock signals synchronized to a reference clock signal. A typical delay-locked loop circuit uses a phase comparator to compare the phase of the reference clock signal with that of the delayed clock signal, and feeds back the comparison result to a delay controller that varies the delay of the delayed clock signal.
FIG. 1 is a block diagram of a conventional delay line. Referring to FIG. 1, the delay line includes a plurality of delay cells 10 connected in series and having the same operation. The delay line is controlled by a control signal SEL[N−1:0] comprising N bits, where N is equal to the number of delay cells, of which N−1 bits are “0” bits and one-out-of-N bits is “1”.
FIG. 2 is a circuit diagram of a delay cell of FIG. 1. Referring to FIG. 2, the delay cell 10 includes a buffer 21, a multiplexer 22, a plurality of terminals IN, PS, RT and OT for inputting and outputting data, and a control terminal SEL receiving a control signal input.
The data input to the IN terminal is transmitted to the PS terminal. The multiplexer 22 transmits data according to the data input to the SEL terminal. For example, when logic 0 is input to the SEL terminal, the data input to the RT terminal is transmitted to the OT terminal. When logic 1 is input to the SEL terminal, the data input to the IN terminal is transmitted to the OT terminal through the buffer 21.
The delay T1 is the time for transmitting the data from the IN terminal to the PS terminal, the delay T2 is the time for transmitting the data from the PS terminal to the OT terminal, and the delay T3 is the time for transmitting the data from the RT terminal and the OT terminal. When “0” is input to the SEL terminal, the step delay of the delay cell 10 becomes equal to the sum of the delays T1 and T3. When “1” is input to the SEL terminal and when T2 is the same as T3, the step delay of the delay cell 10 becomes equal to the sum of the delays T2 and T1.
In conventional delay line circuits, the improvement of the characteristics of the output signal often requires a complex design or results in undesirably high power consumption. On the other hand, the reduction of power consumption or circuit size often degrades the characteristics of the output signal. Therefore, the need exists for a delay cell for use in a delay line circuit to provide improved performance with reduced power consumption.